The invention is based on a method for precharging memory cells of a dynamic semiconductor memory and on a semiconductor memory of the generic type. In dynamically clocked semiconductor memories, the problem can arise that the charges (information) stored in the memory cells are not renewed (refreshed) as expected in particular when the operating voltage is switched on (power-up). This may be the case particularly when a very large number of memory cells have to be simultaneously subjected to charge reversal.
This memory behavior is caused by the fact that the required charging current cannot be applied by the plate generator simultaneously for all or for the majority of the memory cells. Each memory cell is formed with a small cell capacitor (plate capacitor) integrated in the substrate of the semiconductor memory. When rewriting the cell contents, therefore, it is also necessary to change the charge of the cell capacitors in the substrate. If the sign of these charges is not distributed statistically uniformly, but rather is so pronounced that the same voltage is written to the majority of the memory cells, then there is a significant charge entry into the counter electrode of the cell capacitors, the so-called plate. The charge entry alters the plate voltage, which entails a corresponding displacement current. The displacement current has to be compensated for by the on-chip voltage supply system for the plate voltage, in this case by the plate generator.
The magnitude of the displacement current can easily be calculated since the displacement current is proportional to the number of memory cells to be subjected to charge reversal that are to be subjected to charge reversal within a unit of time.
The performance of the plate generator is generally optimized in such a way that it can supply all the displacement currents that occur in normal operation of the semiconductor memory. Larger dimensioning would have the disadvantage of requiring a larger chip area for the realization, which would accordingly drive up the fabrication costs. Therefore, for the dimensioning of the plate generator, the performance is defined according to the maximum current occurring in regular operation, which current can be determined by the number of memory cells, the size of the cell capacitors, the charging time constant and the maximum voltage swing that occurs.
Thus, by way of example, in the case of an SDRAM having 16 memory cells to be subjected to charge reversal each with a capacitance of 40 fF, a current of 115 xcexcA flows given a charging time of 10 ns and a voltage swing of 0 to 1.8 volts.
In a special case, changed conditions are present directly after the switch-on (power-up) of the operating voltage. In this case, all the memory cells of the semiconductor memory are capacitively raised to the plate voltage of 0.9 volts during charging of the plate with the corresponding cell capacitors, in order to remain at the example mentioned above.
If, before the cells are written to, first a refresh of the memory cells is carried out, then the assigned sense amplifier interprets, for example, a voltage of 0.9 volt as logic 1 and then attempts, for example, to charge all the memory cells to the operating voltage of 1.8 volts, for example. Since, by way of example, in the case of an SDRAM memory PC 100 having 32 k memory cells, with 70 ns, the refresh proceeds much faster than a write operation, the current to be supplied by the plate generator rises in an extreme fashion. Thus, in this case, by way of example, with the SDRAM having 32 k memory cells each of 40 fF and a voltage swing of 0.9 to 1.8 volts, a current of 16.8 A would become necessary.
A solution to this problem has not been disclosed heretofore. As already mentioned above, enlarging the plate generator would entail corresponding cost disadvantages. In contrast, if the plate generator is not enlarged, then the plate voltage can decrease during the refresh operation. During a subsequent write operation directly after the refresh operation, the amplitude of the cell signal decreases as a result, since the memory cells can no longer be charged to the full value of the supply or operating voltage.
If it is assumed, for example, that the plate has been charged to 1.8 volts during the refresh operation, then a voltage difference between the plate and the memory cell of 0 volts is obtained when writing a logic 1, which corresponds to the operating voltage of 1.8 volts. If the plate relaxes, that is to say discharges by the time of reading to 0.9 volt, then the memory cell is also discharged to 0.9 volt. At this limit value, it is then chance that decides whether the sense amplifier now interprets this value as logic 0 or 1. However, such uncertainty is undesirable and unacceptable to a user of the semiconductor memory.
It is accordingly an object of the invention to provide a method for precharging memory cells of a dynamic semiconductor memory during power-up and a semiconductor memory that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, in which an improved signal evaluation is made possible even in the case of extreme operating states.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for precharging memory cells of a dynamic semiconductor memory. The method includes controlling the memory cells disposed in rows and columns through use of word lines and bit lines, using sense amplifiers for reading out, amplifying and returning again information stored in the memory cells in a refresh cycle, and during a switch-on of an operating voltage, precharging the memory cells to a predetermined potential.
The inventive method has the advantage that the above-mentioned disadvantages can be avoided or cannot occur. In this case, it is regarded as particularly advantageous that the plate generator does not have to be amplified and yet can even supply the current flowing in the aforementioned special case after the power-up. What is also achieved by the improved evaluation of the cell signal in the case of a dynamic semiconductor memory is that the errors during reading are minimized and a higher reliability is thus obtained for the stored information.
It is regarded as particularly advantageous that the memory cells are precharged to 0 volts or alternatively to the potential of the operating voltage. The plate generator can advantageously be optimally dimensioned to these defined values taking account of the charging time, so that it is able to supply the required current for each operating mode.
A further alternative solution is also seen in the fact that approximately half of the memory cells are precharged to 0 volts and, respectively, approximately half of the memory cells are precharged to the operating voltage. This ensures that the average current becomes lower and, as a result, the plate generator can be further optimized.
It is expedient, moreover, to control the memory cells with the aid of the assigned sense amplifiers. This can be done in a simple manner by the signals on the control lines that control the sense amplifiers.
In principle, the memory cells can be controlled by the sense amplifiers in two advantageous ways. One expedient alternative is for the word lines to be activated, the two equalizers and the isolation switches of a sense amplifier to be conducting and switched off, respectively, the N-FET set signal to be switched to 0 volts and the P-FET set signal to be switched to the potential of the operating voltage. The selection signal (column select signal) is switched off. Thus, the sense amplifier has to decide the direction in which it toggles. Consequently, one half of the memory cells is precharged to the operating voltage and the other half of the memory cells is precharged to 0 volts (ground). As a result, the statistically average current that has to be supplied by the plate generator is relatively low.
The second alternative solution consists in the word lines are activate, the two equalizers being switched on, the bit lines thereof being put at 0 volts and at the potential of the operating voltage, respectively, and the isolation switches being turned off. This configuration isolates the interior of the sense amplifiers, so that signals cannot exercise any influence in the interior of the sense amplifiers. All the memory cells are then advantageously precharged to 0 volts and to the operating voltage VBLH, respectively.
In the case of the semiconductor memory, the application in a DRAM module is regarded as an advantageous solution since, with this type of memory, the memory cells require a cyclic refresh signal in the case of which the stored information is continuously read out and read in again in amplified fashion.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory. The memory contains word lines having word line pairs, bit lines, a multiplicity of memory cells disposed in rows and columns and connected to and controlled by the word lines and the bit lines, and sense amplifiers. A respective word line pair is connected to a respective sense amplifier. Each of the sense amplifiers has two equalizers, four isolation switches, N-FET and P-FET switches, and set signals for the N-FET and P-FET switches. The sense amplifiers precharge the memory cells to an operating voltage or to 0 volts during a switch-on of the operating voltage.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for precharging memory cells of a dynamic semiconductor memory during power-up and a semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.